This invention relates generally to floating point processors used in computers and more particularly to a method and apparatus to multiply floating point numbers.
As it is known in the art, many applications in computers require the use of numbers that are not integers. There are several ways in which nonintegers can be represented in computers. The most common approach is the so-called floating-point representation in which a number is divided into separate sections. One section of a floating-point number is referred to as a fraction which represents the precision of the number and the another section is referred to as an exponent. A third section is a bit for the sign of the number or operand.
One operation commonly performed in floating-point processors is the multiplication of two floating-point numbers. One approach used to multiply two floating-point numbers is to provide the floating-point numbers i.e. multiplicand and multiplier to a multiply array comprising a plurality of rows of carry-save adders which determine partial products of the multiplication operation in redundant form. The result of each row of the array is a sum and a carry vector which is shifted prior to being combined with a more significant sum and carry vector in the next row of the array. The sum is shifted by M positions in order to align the sum vector with the next sum vector while the carry vector is shifted by M-1 positions. After the resulting carry vectors and sum vectors propagate to each of the rows of the array, a final carry vector and sum vector are provided from the last row of the array. To obtain the final result, the final sum and carry vectors are added together to provide the product of the multiplication operation. A floating point multiplication of two floating point operands, each with N bits, produces a result of 2N bits of fraction. The desired result is the product normalized such that the fraction is between one-half and one and then correctly rounded to N fraction bits. Since the least significant N bits of the full product are not included in the fraction results, the width of the multiplier might need only to be n+2 bits wide. The additional two bits accounts for rounding bits for the fraction results greater than one-half and less than one-half so long as the contributions are partial product bits in the n -2 least significant bit positions to the n+2 most significant bit positions is included.
One problem that exists, therefore, is in not duplicating the entire multiplier array for the lower N-2 bits of the multiplication result since such a duplication in the multiplier array will reduce the speed of the multiplication operation and will require a large amount of logic circuits to implement.
It is also known that there are techniques for reducing the size of the multiplier array particularly with respect to the most significant bits of the result. So-called "booth" coding is often used in order to reduce the total number of partial products and resulting summations which must be performed on a multiplication of two floating-point operands. By reducing the partial products which are summed such as with an odd-even booth encoding scheme, the number of carry-save adder delays need to determine the product are concomitantly reduced, but it is necessary, nevertheless, to account for the product data which is shifted off the array in order to determine what contribution, if any, to the final rounding result would be made by the lower order bits of the lower order product.
One technique known to account for a contribution from the lower order product used on the Alpha 21064 microprocessor manufactured by Digital Equipment Corp. assignee of the present invention, uses a half adder to add two of the initial partial products in the first row of the multiplier array. The sum and carry from the half adder in the multiplier array as well as bits of the initial partial products were fed to a lower order array of two levels of carry-save adders and carry chain. This solution had some drawbacks since it required an extra row of carry save adder delay because only two initial partial products are summed by the initial half adder. This increases the overall propagation length of the array and thus reduces performance.